Integrated circuit modules of the type mentioned above, such as multichip modules (MCMS), are shown and described in U.S. Pat. No. 4,783,695, "Multichip Integrated Circuit Packaging Configuration and Method," issued Nov. 8, 1988, and in U.S. Pat. No. 4,918,811, "Multichip Integrated Circuit Packaging Method," issued Apr. 24, 1990, both assigned to the assignee of the present invention and herein incorporated by reference. Such so-called high density interconnect (HDI) structures, which may be built up in an integrated circuit module by means of multiple layer sequences stacked over the electrical or electronic circuit component or components and the substrate, provide the capability to interconnect the components, such as VLSI chips, to achieve improved integration. In such a module, each sequence includes at least a dielectric film, such as a polymer, and a metal layer that overlies the film and that makes the desired intrachip and interchip connections. Typically, the top face of the module is aligned with respect to the patterning system during the fabrication of the metallized interconnect, such as by positioning at least two reference points on the face of the module, to permit positioning of the desired interconnection pattern to be fabricated on the top or aligned face and thereby ensure that the desired electrical connections are achieved. One possible alignment technique is described in U.S. Pat. No. 4,835,704, "Adaptive Lithography System to Provide High Density Interconnect," issued May 30, 1989, assigned to the assignee of the present invention and herein incorporated by reference.
Various methods of fabrication have been devised to produce such modules, as disclosed in the aforementioned patents. Likewise, structures for interconnecting modules have been devised to achieve more interconnections and higher integration than previously available, such as disclosed in U.S. Pat. No. 5,019,946, "High Density Interconnect with High Volumetric Efficiency," issued May 28, 1991, assigned to the assignee of the present invention and herein incorporated by reference. As disclosed in the last recited patent, interconnected integrated circuits packaged at a high density are fabricated with a plurality of substrates where each substrate has metal edge contact sites and the substrates are joined together in a stack held together tightly, such as by bolts or by a thermoplastic adhesive. In such a stack, a metal interconnection pattern electrically connects or couples the integrated circuits on different substrates. Thus, in the fabrication of these modules it is desirable to shape a metal interconnection pattern on a face of the module other than the top or aligned face.